The invention relates to a method for controlling a converter with distributed energy stores.
DE 101 03 031 A1 discloses a converter with distributed energy stores. An equivalent circuit of a converter such as this is shown in more detail in FIG. 1. According to this equivalent circuit, this known converter has three phase modules, which are each annotated 100. These phase modules 100 are each electrically conductively connected on the DC voltage side to a positive and a negative DC voltage busbar P0 and N0. In the case of a voltage intermediate-circuit converter, a series circuit of two capacitors C1 and C2, across which a DC voltage Ud is dropped, would be connected between these two DC voltage busbars P0 and N0. A connection point between these two capacitors C1 and C2, which are electrically connected in series, forms a virtual neutral point O. Each phase module 100 which forms a bridge arm of the polyphase converter has an upper and a lower bridge arm element, which are referred to in the following text as the respective valve arms T1, T3 and T5 as well as T2, T4 and T6, since the bridge arm elements each represent a converter valve of the polyphase converter with distributed energy stores. Each of these valve arms T1 to T6 has a number of two-pole subsystems 10 which are electrically connected in series. In this equivalent circuit, four of these subsystems 10 are shown. The number of subsystems 10 per valve arm T1, . . . , T6 is, however, not restricted to this illustrated number. Each junction point between two valve arms T1 and T2; T3 and T4 as well as T5 and T6 of a phase module 100 forms a respective connection L1, L2 and L3 on the AC voltage side of a phase module 100. Since, in this illustration, the converter has three phase modules 100, a three-phase load, for example a polyphase motor, can be connected to their connections L1, L2 and L3 on the AC voltage side, also referred to as load connections.
FIG. 2 shows an equivalent circuit of one known embodiment of a two-pole subsystem 10 in more detail. The circuit arrangement shown in FIG. 3 represents a functionally completely equivalent variant. Both embodiments of a two-pole subsystem 10 are known from DE 101 03 031 A1. These known two-pole subsystems 10 each have two semiconductor switches 1 and 3 which can be turned off, in each case two diodes 2 and 4 and in each case one unipolar energy storage capacitor 9. The two semiconductor switches 1 and 3 which can be turned off are electrically connected in series, with this series circuit being connected electrically in parallel with the energy storage capacitor 9. One of the two diodes 2 and 4 is electrically connected in parallel with each semiconductor switch 1 and 3 which can be turned off such that these diodes 2 and 4 are connected back-to-back in parallel with the corresponding semiconductor switch 1 or 3 which can be turned off. The unipolar energy storage capacitor 9 in the subsystem 10 consists either of a capacitor or of a capacitor bank composed of a plurality of such capacitors having a resulting capacitance C0. The connection point between the emitter of the semiconductor switch 1 which can be turned off and the anode of the diode 2 forms a connecting terminal X1 of the subsystem 10. The connection point between the two semiconductor switches 1 and 3 which can be turned off and the two diodes 2 and 4 forms a second connecting terminal X2 of the subsystem 10.
In the embodiment of the two-pole subsystem 10 shown in FIG. 3, this connection point forms the first connecting terminal X1. The connection point between the collector of the semiconductor switch 1 which can be turned off and the cathode of the diode 2 forms the second connecting terminal X2 of the subsystem 10.
In both illustrations of the two embodiments of the two-pole subsystem 10, Insulated Gate Bipolar Transistors (IGBT) are used as the semiconductor switches 1 and 3 which can be turned off as shown in FIGS. 2 and 3. It is likewise possible to use MOS Field-Effect Transistors, also referred to as MOSFETs. It is also possible to use Gate Turn Off Thyristors, also referred as GTO thyristors, or Integrated Gate Commutated Thyristors (IGCT).
According to DE 101 03 031 A1, the two-pole subsystems 10 in each phase module 100 of the converter as shown in FIG. 1 are switched to a switching state I, II and III. In the switching state I, the semiconductor switch 1 which can be turned off is switched on, and the semiconductor switch 3 which can be turned off is switched off. The terminal voltage UX21 which is present at the connecting terminals X1 and X2 in the two-pole subsystem 10 is therefore equal to zero. In the switching state II, the semiconductor switch 1 which can be turned off is switched off, and the semiconductor switch 3 which can be turned off is switched on. In this switching state II, the terminal voltage UX21 which is present is equal to the capacitor voltage UC across the energy storage capacitor 9. In the switching state III, both semiconductor switches 1 and 3 which can be turned off are switched off, and the capacitor voltage UC across the energy storage capacitor 9 is constant.
In order to allow this converter to operate in redundant form with distributed energy stores 9 as shown in FIG. 1, it is necessary to ensure that a faulty subsystem 10 is permanently short-circuited at its terminals X1 and X2. This means that the terminal voltage UX21 of the faulty subsystem 10 is zero irrespective of the current direction through the terminals X1 and X2.
The failure of one of the semiconductor switches 1 and 3 which can be turned off and are present in the subsystem 10, or of an associated control circuit, results in this subsystem 10 not operating correctly. Further possible causes of malfunctions are, inter alia, faults in the associated control circuit for the semiconductor switches, their power supply, communication and measured-value detection. That is to say, the two-pole subsystem 10 can no longer be controlled as desired in one of the possible switching states I, II or III. The short-circuiting of the subsystem 10 at its connections X1 and X2 means that no more power is supplied to this subsystem 10. This reliably precludes consequential damage such as overheating and fire resulting from continued operation of the converter.
A conductive connection like a short circuit such as this between the connecting terminals X1 and X2 of a faulty two-pole subsystem 10 has to reliably carry at least the operating current of one valve arm T1, . . . , T6 in the phase module 100 in which the faulty two-pole subsystem 10 is connected, without overheating. DE 10 2005 040 543 A1 discloses how a faulty subsystem 10 can be reliably short-circuited in order that this known converter with distributed energy stores can continue to be operated in a redundant form.
The following explanation is based on the assumption that the energy storage capacitors 9 in all of the two-pole subsystems 10 each have the same voltage UC. Methods for initially producing this state and for maintaining it during operation are likewise known from DE 101 03 031 A1. FIG. 4 shows a graph of a profile of the potential difference UPL between the terminal P of a phase module 100 and a grid connection L, plotted against the time t. FIG. 5 shows a graph of a profile of the potential difference ULN between the terminal L and the potential at the terminal N, plotted against the time t. According to these potential profiles UPL and ULN, in each case one subsystem of the eight two-pole subsystems 10 of the valve arms T1 and T2 is connected or disconnected at each of the times t1, t2, t3, t4, t5, t6, t7 and t8. Switching on in this case corresponds to a change from the switching state I to the switching state II. Turning off corresponds to a change from the switching state II to the switching state I. These two graphs each show one period TP of a fundamental oscillation of the potential profile uL0 (FIG. 6) between the load connection L and the virtual neutral point O of a phase module 100 of the converter with distributed energy stores 9, for the potential profiles UPL and ULN.
FIG. 6 shows a profile of the difference between the potential profiles ULN and UPL as shown in FIGS. 4 and 5, in the form of a graph plotted against the time t. This resultant potential profile ULO occurs between a connection L1, L2 or L3 on the AC voltage side of a phase module 100 in the converter with distributed energy stores 9 as shown in FIG. 1 and an arbitrarily selected potential of a virtual neutral point O of a voltage intermediate circuit having two capacitors C1 and C2. Corresponding components of harmonics or DC voltage components in each of the output voltages ULO of the phase modules 100 in the polyphase converter with distributed energy stores 9 as shown in FIG. 1 are resolved in the case of a balanced polyphase voltage system in the difference voltages between in each case two phase-shifted output voltages UL10, UL20 or UL30. These two potential profiles UPL and ULN likewise show that the sum of the potentials at any time is 4·UC. This means that the value of the DC voltage Ud between the DC voltage busbars P0 and N0 always corresponds to a constant number of subsystems 10 in the switching state II multiplied by the value of the capacitor voltage UC across the capacitor 9. In the situation illustrated by way of example, this number corresponds to the number of two-pole subsystems 10 in the valve arms T1, . . . , T6 in the converter as shown in FIG. 1.
DE 10 2005 045 091 A1 discloses a method for controlling a converter with distributed energy stores as shown in FIG. 1, by means of which the balance conditions are maintained in the event of a malfunction of at least one subsystem in a phase module of this converter. According to this known method, one valve arm of one of the three phases in which one or more of the two-pole subsystems is or are faulty is first of all determined. Each faulty subsystem is controlled such that the amplitude of the terminal voltage is in each case zero. A number of subsystems corresponding to the number of determined two-pole subsystems in a further valve arm of the faulty phase module are controlled such that the amplitude of the terminal voltage is in each case equal to a capacitor voltage. This control of the subsystems in the faulty phase module is likewise carried out in subsystems in the valve arms of the sound phase modules.
FIG. 7 shows a graph of a profile of the potential difference UPL1 between the terminal P in a phase module 100 and a load connection L in a phase module 100, plotted against the time t, with one faulty two-pole subsystem 10 in the lower valve arm T2 and T4 and T6 in a phase module 100. FIG. 8 shows a graph of a profile of the potential difference UL1N between the terminal L and the potential of the terminal N, plotted against the time t. As can be seen from the profile of the potential difference UPL in FIG. 7, a subsystem 10 in each upper valve arm T1 and T3 and T5 of each phase module 100 is controlled such that its terminal voltage UX21 is always equal to the capacitor voltage UC across the energy storage capacitor 9. Of the four subsystems 10 illustrated by way of example in each upper valve arm T1 and T3 and T5, there are now only three remaining subsystems 10 which are connected and disconnected. As can be seen from the time profile of the potential difference ULN of each lower valve arm T2 and T4 and T6 in each phase module 100, in each case one of the four subsystems 10 illustrated by way of example is controlled such that its terminal voltage UX21 is always equal to zero. As shown in FIG. 1, of these lower valve arms T2, T4 and T6 in the three phase modules 100, the valve arm T2 has a faulty two-pole subsystem 10, identified by shading. The value of the amplitudes of the voltage ULN of each valve arm T2, T4 and T6 can therefore now be only at most 3·UC. This known method results in the number of subsystems 10 used in the event of a fault being equal to the number of subsystems 10 used when no faults are present. The profile of the amplitude of the sum of the potential differences UPL and ULN is shown by means of a dashed line in the graph in FIG. 8. In comparison to the situation when there are no faults, the voltages UL10, UL20 and UL30 each have a lower maximum amplitude when a fault is present. In the illustrated example, these voltages UL10, UL20 and UL30 when no fault is present have a maximum voltage amplitude of ½·Ud each, while in contrast the maximum amplitude when a fault is present is only ⅜·Ud. This means that this known method results in a balanced three-phase voltage system, with a lower maximum amplitude, when a fault is present.
FIG. 9 shows a profile of the difference in the voltage differences UPL and ULN as shown in FIGS. 7 and 8, plotted against the time t. As can be seen from this time profile of the potential between the load connection L1 or L2 or L3 and a virtual neutral point O, this potential no longer oscillates symmetrically about a null position. This null position is shifted through ⅛·Ud. This means that this potential profile has a DC component.